1. Field of the Invention
The present invention relates to a clock switching circuit for changing for input data a clock having a fixed phase to a clock having a different phase. The present invention can be applied, for example, for an elastic storage controller in a signal transceiver for an automatic switch.
2. Related Arts
Conventionally, a phase synchronization method using an elastic storage control method is employed for various types of bit phase synchronization circuits.
An overview of the elastic storage control method will now be given. In the communication of a signal between asynchronous systems, a reception side employs a clock received from a transmission side to temporarily store received data in a memory, and reads the data from the memory in the order in which they were received, in accordance with a system clock that is internally used on the reception side. Thus, on the reception side, the handling of the input data can be performed in synchronization with the system clock.
However, since it is a premise of a conventional condition that an input clock and a system clock should have the same clock frequency, one elastic storage controller handles only one clock frequency.
Specifically, unless the frequency of an input clock that is synchronized with input data is identical to the clock frequency that was set when the elastic storage controller was designed, the bit phase synchronization function is not performed satisfactorily, and only one type of relationship is established between the input clock and the system clock.
At the present time, when data are exchanged at various transmission speeds, signal transceivers that can handle such data (data for which different clock frequencies are used) have been developed; however, conventionally, a single elastic storage controller is not capable of adequately coping with data communications for which various clock frequencies are employed. In other words, a different elastic storage controller is required for each type of clock frequency used for input data.
This problem is also due to the lack of an elastic storage controller that can cope with situations wherein the clock frequencies of input data differ from the frequencies of system clocks, especially when the frequencies of the system clocks are higher.
Therefore, there is a demand for a clock switching circuit that can switch clocks even when the frequency of a post-switched clock is higher than a pre-switched clock.
There is also a demand for a clock switching circuit that can change several different clock frequencies for input data to a post-switched clock having a predetermined frequency.
To achieve the above objective of the present invention, according to a first aspect of the invention, a clock switching circuit comprises:
writing means for generating a write address based on a pre-switched clock, and for employing the write address to store input data in storage means; and
reading means for generating a read address based on a post-switched clock that is independent of the pre-switched clock, and for employing the read address to read data from the storage means, thus changing a clock that is synchronized with the data,
wherein the frequency of the post-switched clock is higher than the frequency of the pre-switched clock, and
wherein, upon the receipt of the post-switched clock, the reading means updates or maintains the read address, in accordance with a ratio of the frequency of the pre-switched clock to the frequency of the post-switched clock.
According to a second aspect of the invention, a clock switching circuit comprises:
writing means for generating a write address based on a pre-switched clock, and for employing the write address to store input data in storage means; and
reading means for generating a read address based on a post-switched clock that is independent of the pre-switched clock, and for employing the read address to read data from the storage means, thus changing a clock that is synchronized with the data,
wherein a plurality of frequencies are employed for the pre-switched clock, and the frequency of the post-switched clock is equal to or higher than the highest frequency of the pre-switched clock, and
wherein, when the frequency of the pre-switched clock that is input is lower than the frequency of the post-switched clock, upon the receipt of the post-switched clock the reading means updates or maintains the read address, in accordance with a ratio of the frequency of the input pre-switched clock to the frequency of the post-switched clock.